This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a redundant row or block of memory cells. It provides a method and structure for substituting a redundant row or block of memory cells for a faulty row or block.
Redundant memory cells are provided to increase the yield of memory devices. A redundant cell, row, or block of cells can be used to salvage devices having fewer than a specified number of defective cells, and thus increase yield. As memories become larger, the yield of perfect memory chips becomes lower, since having a larger number of cells on a silicon chip provides more opportunity for defective cells. Also, smaller size makes individual cells more fragile if there is not an accompanying increase in precision of cell fabrication. Programmable Read-Only Memory (PROM) devices are widely used in semiconductor applications. One type of PROM is programmed by opening fuses in selected memory cells. Fuse array PROMs are particularly susceptible to defects because the fuses are thin strands of metal and must have reliable characteristics such as width, thickness, and sheet resistivity so that they can be opened (blown) during programming but function reliably as a conducting wire if not opened.
Various methods for providing redundant memory are known in the art. Some circuits provide groups of individually addressable redundant memory cells, some provide single or multiple rows or columns of cells, and some provide blocks of memory cells and accompanying circuitry. Goldberg, in U.S. Pat. No. 3,995,261 describes a method for shifting the address of individual cells to avoid defective cells. Sumilas, et al., U.S. Pat. No. 3,753,244 stores in the integrated circuit the address of a defective row, and when the defective row is addressed uses a comparator to deselect the entire memory and select the redundant row. Sander, U.S. Pat. No. 3,654,610 provides a code converter, translating the address of a memory row to one of a series of possible intermediate codes which can be chosen to avoid locations of faulty cells. McKenny, U.S. Pat. No. 4,281,398, replaces an entire block of memory and the accompanying circuitry when the block is found defective.
Software is also used to replace units of defective memory with redundant memory. Choate, et al., in U.S. Pat. No. 4,047,163 describes a method which stores the row and column address of every defective cell and when a defective cell is addressed, the storage means generates signals which cause a corresponding cell in the redundant row or column to be selected in place of the defective cell.
Providing redundancy in memory devices requires extra circuitry and extra space on the device, and if gate delays result from the circuitry used to address redundant memory, providing such redundancy slows the operation of the device. It is an object of this invention to provide a redundant memory structure and method for disabling and replacing defective memory in a PROM such as a fuse array, which is programmed by open-circuiting memory cells. Another object is to provide sufficient redundancy to significantly increase yield without significantly slowing the operation of the circuit or increasing the size of the device.